1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly, to low power dissipating sense amplifying circuitry.
2. Description of the Related Art
As is well known in the art, memory devices are generally array structures having a multiplicity of columns and a multiplicity of rows. A memory cell, located at an intersection of a selected row and column, is addressed by activating the control signals for the associated row and column. Once the digital data stored at the memory cell is read, a small read current is sensed. In order to produce a readable data signal representing the digital data stored at the memory cell, a sense amplifier is typically implemented to amplify a small voltage difference built from a difference between the small read current and a reference current. The performance of a sense amplifier strongly affects both memory access time, and overall memory power dissipation. As with other integrated circuits today, memory devices are required to increase speed, reduce space and maintain low power dissipation.
FIG. 1 illustrates an example of a conventional memory array 100. The memory array 100 comprises 8 memory blocks (memory block 101, memory block 102, . . . memory block 108), a reference cell circuit 110, and 4 pass gates (MYS0, MYS1, MYS2, and MYS3). Each memory block has 256 memory cells that are arranged in 4 columns with 64 memory cells per column. A memory block further includes 4 column select gates, a column select control signal, a read/write control signal, and 64 word lines (WL). The memory array 100 is connected to a sense amplifier via the reference data line (RDL) and the data line (DL). For example, the memory cell M0 of the memory block 101 can be addressed by raising the word line WL1—0, the column select control signal SEL0, and the pass gate control signal YS0 to the value of a rail voltage source VDD while keeping the rest of the column select control signals, word lines, and the read/write control signals of the memory array 100 to ground. After the memory cell M0 is read, a small read current representing the digital data stored at the memory cell M0 is sensed and output to the DL via the column select gate MSEL00 and the pass gate MYS0. The small read current on the DL is in turn passed to a sense amplifier. A small reference current can be obtained via the RDL of the reference cell circuit 110 of the memory array 100.
FIG. 2 is a conventional sense amplifier 200 which can be connected to the memory array 100 via the DL and the RDL. As shown, the sense amplifier 200 comprises 5 parts: the circuit 220, the circuit 230, the circuit 240, the circuit 250, and the circuit 260. The circuits 220 and 230 are used to convert the small read current obtained from the DL and the small reference current obtained from the RDL into a small voltage amplitude and a small reference voltage amplitude on the signal lines SA1 and SA2, respectively. The circuit 240 and 250 are two amplifying circuits, and the circuit 260 is an inverting circuit. VDD is a rail voltage source. The n-channel transistors 221 and 231 are always on by the BIAS control signals. Two identical loading transistors 222 and 232 act as large resistors. A small reference voltage amplitude is built on the signal line SA2. The small voltage amplitude on the signal line SA1 depends upon the digital data stored at the addressed memory cell. If the digital data stored at the memory cell is “1”, the small voltage amplitude on the signal line SA1 is slightly smaller than the small reference voltage amplitude. Otherwise, the small voltage amplitude on the signal line SA1 is slightly larger than the small reference voltage amplitude. The circuit 240 is a differential amplifier that is composed of five transistors 241, 242, 243, 244 and 245. The p-channel transistors 243 and 244 form a well know current mirror. The n-channel transistor 241 and 242 are gain transistors, which amplifies the small voltage difference between the small voltage amplitude on the signal line SA1 and the small reference voltage amplitude on the signal line SA2. The n-channel transistor 245, activated by the BIASA control signal, limits the current consumption of the differential amplifier 240. When the small voltage amplitude at the signal line SA1 is about 1.25V, the transistor 241 is on. Consequently, the output of the differential amplifier 240 at the signal line SO0 will be pulled down to “0”. The circuit 250 is a complementary metal-oxide-semiconductor (CMOS) amplifying circuit, which includes one n-channel transistor 251 and one p-channel transistor 252. When the input of the circuit 250 (from the signal line SO0) is “0”, the output of the circuit 250 at the signal line SAB will be “1”, which is then inverted again by the circuit 260. The resulting output at the signal line SA will be “0”.
In order to match the large parasitic capacitance loading from the DL of the memory array 100, the reference cell circuit 110 has to use many dummy cells. As shown in FIG. 1, the number of the dummy cells and the reference cell of the reference cell circuit 110 needs to equal the number of the memory cells at a column of the memory array 100. As a result, the reference cell circuit 110 of the memory array 100 occupies more space in the layout. The use of a differential amplifier in the conventional sense amplifier 200 causes it to consume more power. Especially in the page mode, when many sense amplifiers have to be triggered at the same time, the reference cell circuit space occupation and sense amplifier power dissipation problems will become even more severe.
In view of the foregoing, there is a need for a sense amplifier that is low power consuming, occupies less space, and maintains fast accessing speed.